JEDEC JESD82-18A PDF

JEDEC JESD82-18A – STANDARD FOR DEFINITION OF THE CUA877 AND CU2A877 PLL CLOCK DRIVERSFOR REGISTERED DDR2 DIMM APPLICATIONS

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the CUA877 and CU2A877 PLL clock devices for registered DDR2 DIMM applications.The purpose is to provide a standard for the CUA877 and CU2A877 PLL clock devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.