ESD SP5.4.1 PDF
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For Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing Device Level
| Published by | Publication Date | Number of Pages |
| ESD | 2018 | 28 |
ESD SP5.4.1 – For Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing Device Level
ESD SP5.4.1-2017 defines procedures to characterize the latch-up sensitivity of integrated circuits triggered by fast transients.
| Published | 2018 |
|---|---|
| ISBN(s) | 158537296X |
| ANSI | ANSI Approved |
| Number of Pages | 28 |
| File Size | 1 file , 740 KB |
| Note | This product is unavailable in Russia, Ukraine, Belarus |
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